# Create a virtual clock for interfacing with an external device create_clock -name v_clk -period 2.0 Use code with caution. Clock Properties: Jitter, Latency, and Skew
Some complex arithmetic blocks (like multipliers or dividers) require more than one clock cycle to stabilize their outputs. A multicycle path exception tells the tool to open the setup or hold check window across multiple clock edges. synopsys timing constraints and optimization user guide 2021
# Disables timing analysis between asynchronous clock domains set_false_path -from [get_clocks SYS_CLK] -to [get_clocks ASYNC_RX_CLK] # Disable timing on a static, software-configured reset signal set_false_path -from [get_ports soft_reset_n] Use code with caution. Multi-Cycle Paths # Create a virtual clock for interfacing with
The create_clock command is the primary method to define design speed. create_clock -name sys_clk -period 1.0 [get_ports clk] Use code with caution. Which are you seeing (setup, hold, max_transition)
Which are you seeing (setup, hold, max_transition)? Are you dealing with asynchronous clock domains ?