// Instantiate the multiplier eight_bit_multiplier uut ( .a(a), .b(b), .product(product) );
// Inspired by: "High-Speed Multiplier Design" – K. Hwang, 1979 // But fixed the partial product sign extension bug. 8bit multiplier verilog code github
Large propagation delay due to the carry signals rippling through the adder array. Booth’s Multiplier (Radix-2 or Radix-4) // Instantiate the multiplier eight_bit_multiplier uut (
// Zero case #10 A = 8'h00; B = 8'hAA; #10 check_result(0, 170, 0); Booth’s Multiplier (Radix-2 or Radix-4) // Zero case
Simplest, allows the synthesis tool to choose the best architecture based on constraints.
# View waveforms make view </code></pre> <h3>Simulation with ModelSim/Questasim</h3> <pre><code class="language-tcl">vlib work vlog 8bit_multiplier.v tb_8bit_multiplier.v vsim -c tb_eight_bit_multiplier run -all </code></pre> <h3>Synthesis with Yosys</h3> <pre><code class="language-bash">yosys -p "read_verilog 8bit_multiplier.v; synth_ice40 -top eight_bit_multiplier; write_verilog synth.v" </code></pre> <h2>Test Results</h2> <h3>Functional Tests</h3> <p>| Test Case | Input A | Input B | Expected | Result | |-----------|---------|---------|----------|--------| | Basic | 10 | 5 | 50 | ✅ PASS | | Max value | 255 | 255 | 65025 | ✅ PASS | | Zero | 0 | 100 | 0 | ✅ PASS | | Boundary | 128 | 2 | 256 | ✅ PASS |</p> <h3>Performance Metrics (Synthesized for Artix-7)</h3> <p><strong>Combinational Multiplier:</strong></p> <ul> <li>Logic cells: 128</li> <li>Maximum frequency: 150 MHz</li> <li>Latency: 1 cycle</li> <li>Throughput: 150M multiplications/sec</li> </ul> <p><strong>Sequential Multiplier:</strong></p> <ul> <li>Logic cells: 48</li> <li>Maximum frequency: 200 MHz</li> <li>Latency: 8 cycles</li> <li>Throughput: 25M multiplications/sec</li> </ul> <h2>Verification</h2> <p>The testbench performs:</p> <ul> <li>Exhaustive verification for critical ranges</li> <li>Random pattern testing (20+ cases)</li> <li>Boundary condition testing</li> <li>Automatic pass/fail reporting</li> </ul> <h2>Extending to Signed Multiplication</h2> <p>To support signed multiplication, modify the module:</p> <pre><code class="language-verilog">module signed_8bit_multiplier ( input signed [7:0] a, input signed [7:0] b, output signed [15:0] product ); // Use signed arithmetic assign product = a * b; endmodule </code></pre> <h2>License</h2> <p>MIT License - See LICENSE file for details</p> <h2>Contributing</h2> <p>Contributions welcome! Please:</p> <ol> <li>Fork the repository</li> <li>Create feature branch</li> <li>Submit pull request</li> </ol> <h2>References</h2> <ul> <li><a href="https://www.amazon.com/Digital-Design-Principles-Practices-5th/dp/013446009X">Digital Design: Principles and Practices</a></li> <li><a href="https://standards.ieee.org/standard/1364-2005.html">IEEE Standard for Verilog HDL</a></li> </ul> <pre><code> ### 6. GitHub Repository Structure